1. Field of Invention
This invention relates generally to CMOS logic and specifically to minimizing silicon area of PMOS pull-up devices in static logic.
2. Description of Related Art
CMOS logic devices typically include one or more PMOS pull-up transistors connected between a voltage supply and an output node and one or more NMOS pull-down transistors connected between the output node and ground potential. Since the mobility of electrons is greater than the mobility of holes, an NMOS transistor is able to conduct a greater current than a PMOS transistor of the same size. Consequently, in CMOS logic devices, the PMOS pull-up transistors are typically sized much larger than their corresponding NMOS pull-down transistors so that the charge path formed by the PMOS pull-up transistors and the discharge path formed by the NMOS pull-down transistors have equal drive strengths. Maintaining equal drive strengths for the charge and discharge paths is necessary to achieve equal charging and discharging rates of the output node, which in turn provides balanced logic transitions.
A well-known sizing factor used to maintain equal drive strength between a PMOS pull-up transistor and an NMOS pull-down transistor is Beta (.beta.), which is equal the mobility of electrons divided by the mobility of holes. This relationship may be expressed as .beta..congruent..mu..sub.n /.mu..sub.p, where .mu..sub.n is the mobility of electrons, and .mu..sub.p is the mobility of holes. Since the effective drive strength of a transistor is proportional to its width W, the width W.sub.p of a PMOS transistor which provides the same drive strength as an NMOS transistor of width W.sub.n is given by W.sub.p =.beta.W.sub.n.
FIG. 1 shows a conventional CMOS inverter 10 having a PMOS pull-up transistor 11 connected between a supply voltage V.sub.DD and an output node 12, and having an NMOS pull-down transistor 13 connected between the output node 12 and ground potential. The CMOS inverter inverts an input signal provided to the gates of transistors 11 and 13 to generate an output signal B at output node 12. When signal A is logic low, the PMOS pull-up transistor turns on and charges the output node 12 toward V.sub.DD, while the NMOS pull-down transistor 13 turns off and isolates output node 12 from ground potential. When signal A is logic high, the NMOS pull-down transistor 13 turns on and discharges output node 12 toward ground potential, while the PMOS pull-up transistor 11 turns off and isolates output node 12 from V.sub.DD. Since the PMOS transistor 11 is the only pull-up device, the effective drive strength S.sub.p of the pull-up path is determined by the width W.sub.p of the pull-up transistor 11. Similarly, since the NMOS transistor 13 is the only pull-down device, the effective drive strength of the pull-down path is determined by the width W.sub.n of the pull-down transistor 13. Thus, to maintain equal drive strengths S.sub.p and Sn for the respective charge and discharge paths in the CMOS inverter 10, the width of the PMOS pull-up transistor W.sub.p should be equal to the width of the NMOS pull-down transistor W.sub.n times Beta, i.e., W.sub.p =.beta.W.sub.n. For example, if .beta.=2, the width W.sub.p of the PMOS pull-up transistor 11 must be twice the width W.sub.n of the NMOS pull-down transistor 13 to achieve equal drive strengths for the charge and discharge paths.
FIG. 2 shows a conventional NAND gate 20 having two PMOS pull-up transistors 21 and 22 connected in parallel between V.sub.DD and an output node 23, and two NMOS pull-down transistors 24 and 25 connected in series between the output node 23 and ground potential. A first input signal A0 is provided to the respective gates of the transistors 21 and 24, and a second input signal Al is provided to the respective gates of transistors 22 and 25. If either of the input signals A0 or A1 is logic low, the corresponding PMOS pull-up transistor 21 and/or 22 turns on and charges the output node 23 toward V.sub.DD, thereby driving the output signal B to logic high. Since only one of the input signals A0 or A1 must be logic low to drive output signal B to logic high, sometimes only one of the PMOS pull-up transistors 21 and 22 turns on to charge the output node 23 toward V.sub.DD. Thus, the effective drive strength S.sub.p of the charge path is equal to that of one of the PMOS pull-up transistors 21 or 21, i.e., S.sub.p.congruent.W.sub.p.
Both input signals A0 and A1 must be logic high in order to discharge the output node 23 toward ground potential through series-connected NMOS pull-down transistors 24 and 25. Since the resistance of two series-connected transistors is twice that of a single transistor, the effective drive strength of the discharge path through NMOS pull-down transistors 24 and 25 is about one-half the effective drive strength of a single NMOS transistor, i.e., S.sub.n.congruent.W.sub.n /2. Thus, in order to maintain equal drive strengths for the charge and discharge paths of the NAND gate 20, the width of each of the PMOS pull-up transistors 21 and 22 is sized by multiplying the effective NMOS transistor width times Beta, i.e., W.sub.p =.beta.W.sub.n /2.
It is always desirable to reduce the size of a circuit such as, for instance, a CMOS logic device, since any reduction in circuit size typically reduces manufacturing costs and power consumption. Further, reducing the silicon area of a circuit advantageously allows for the circuit to be more easily fabricated using smaller technologies.
While it is desirable to reduce transistor size in order to conserve silicon area, the proper ratio between PMOS and NMOS devices in logic devices must be maintained in order to preserve the balance of the circuit. Otherwise, one input level may overpower the other input level, which in turn could result in erroneous data. Thus, it is desirable to reduce transistor size without sacrificing performance or upsetting the balance of current-carrying capability between PMOS pull-up and NMOS pull-down devices.